This invention relates generally to chip capacitors having a four terminal capacitor lead frame, and related methods of construction. More specifically, the present invention relates to an improved capacitor lead frame design which acts as a transmission line that routes the output current or input current of an electronic device through the capacitor in a manner causing it to act as a four terminal network and further causing the capacitor equivalent series inductance (ESL) and capacitor equivalent series resistance (ESR) both to be dramatically reduced.
There are two primary ceramic capacitor geometries in common use in the industryxe2x80x94the rectangular chip and the feedthrough (often called a discoidal capacitor). The ceramic monolithic rectangular chip (MLC) capacitor (or xe2x80x9cchip capacitorxe2x80x9d) is produced in very high commercial volumes in highly automated facilities. Over the years the cost of ceramic chip capacitors has dropped a great deal. It is now common to purchase certain value chip capacitors for only a few pennies. The ceramic feedthrough capacitor is only produced in a small fraction of the chip capacitor volume. Accordingly, feedthrough capacitor production has not been nearly as automated. In addition, the feedthrough capacitor is inherently more expensive to produce due to drilling and centering the through hole, tighter dimensional control, reduced volumetric efficiency and difficulty in automating the manufacturing process. Typically the cost of a particular value chip capacitor is ten to twenty percent of the cost of an equivalent value discoidal feedthrough capacitor.
FIGS. 1 and 2 illustrate prior art conventional MLC chip capacitors 50 with flat and tombstone mounting. The chip capacitors 50 are of standard construction, including a ceramic dielectric 52 that has disposed therein alternating lay up patterns for a first set of electrode plates 54 and a second set of electrode plates 56 separated by the ceramic dielectric 52 (FIGS. 3 and 4). The first set of electrode plates 54 terminate in a first metallization band 58 exposed at one end of the chip capacitor 50,and the second set of electrode plates 56 is conductively coupled to a second metallization band 60 disposed at an opposite end of the chip capacitor 50.The chip capacitors 50 act as two terminal devices. That is, they are connected from one circuit trace 62 to another circuit trace 64 or from a circuit trace to ground in order to decouple or filter signals from one line to a reference point. In the embodiments of FIGS. 1 and 2, the metallization bands 58 and 60 are soldered or otherwise conductively coupled to pads for the circuit traces 62 and 64 as shown.
FIG. 5 illustrates a typical prior art cylindrical chip-type capacitor 50xe2x80x2 having axial leads 66 and 68. FIG. 6 illustrates a typical prior art chip capacitor 50 having radial leads 70 and 72 extending from the metallization bands 58 and 60.
It has become common practice to use assembled stacks of monolithic ceramic capacitors 50 which form either vertical or horizontal capacitor arrays 74. These are typically installed with a lead frame 76 as shown in FIGS. 7-9. A multiplicity of capacitors 50 are typically stacked up in order the equivalent series resistance (ESR) and also the equivalent series inductance (ESL) of the device. As shown in FIG. 8, the lead frame 76 for the capacitor array 74 includes a lead form 78 for stress relief adjacent to the top ends of mounting feet. An optional outer case 82 may be provided over the array 74 and secured in place by means of an epoxy backfill 84. An equivalent circuit model of generic two terminal capacitor devices as discussed above is shown in FIG. 10. Any of these prior art capacitors may be conformally coated, epoxy encapsulated or enclosed in a mounting case as discussed above.
Why Is Inductance Important?
The inductive properties of capacitors in electronic circuits is becoming increasingly important. As important as these properties are now, it is expected that inductive properties will be even more important as operating speeds increase, active device packaging densities increase, and frequencies of application continue to rise. All other things being equal, device power increases with the square of the frequency. In addition, as active devices increase in complexity, the pin count for power distribution and grounding increases. As the number of pins increase, the total lead length and thus associated inductances increase, requiring the increased use of decoupling capacitors to handle system issues associated with the greater inductance. As early as the mid 1980 s, bypass applications of capacitors were estimated to be up to 85% of the U.S. capacitor market (Rappaport, Andy, xe2x80x9cCapacitors, xe2x80x9d Electronic Design News, Vol. 27 (20), Oct. 13, 1982, pp. 104-113, 115-116, 118). This percentage has likely increased.
Following are examples of some capacitor applications where capacitor equivalent series inductance (ESL) is very important:
1. Low ESL/Low ESR capacitors are increasingly needed as ripple current filters in the inputs and/or outputs of switch mode power supplies (SMPS), buck regulators, power converters and DC to DC converters. The switching frequency of such devices has been increasing over the last ten years which improves their efficiency and packaging density.
2. Low inductance capacitors are needed to match the fast turn-on/off times of silicon-controlled rectifiers, used in a variety of equipment, including: railway signaling units, spike suppression circuitry, power supply filters, and motor control equipment.
3. Capacitors are used to reduce the xe2x80x9cDelta-Ixe2x80x9d noise in high speed computers (Chen, Howard C. and Schuster, Stanley E., xe2x80x9cOn-Chip Decoupling Capacitor Optimization for High Performance VLSI Design,xe2x80x9d Proceedings. VLSI Tech Systems Applications Conference, 1995, pp. 99-103; Travis, Bill, xe2x80x9cUse Local Bypass Capacitors to Meet Rigorous High-Speed-System Demands,xe2x80x9d EDN [European Edition], Vol. 40 (1), Jan. 5, 1995, pp. 63-66, 68, 70; Martin, Arch G., xe2x80x9cMultilayer Ceramic Capacitors Beat the Inductance Blues,xe2x80x9d Electronic Design, Vol. 29 (11), May 28, 1981, pp. 99-102.). In a bypass application, decoupling capacitors are added a) to reduce switching noise between the power supply and the IC input/output (I/O) buffers, b) to reduce voltage drops across the power supply caused by interconnect inductances, and c) to reduce radiated EMI noise.
The amount of induced EMF can be given by the equation:
Induced EMF=L (di/dt)
To reduce the total EMF, one approach is to reduce inductance. This is usually accomplished first by attempting to put decoupling capacitors on the substrate itself in parallel with current-carrying conductors on the microprocessor. This approach is often not feasible which leads to the addition of one or more decoupling chips to be put nearby. This alternative may require signal fan-out connections on the surface of the module. This allows the uppermost internal layers to be dedicated to capacitor-to-chip power connections to reduce switching noise that occurs when many drivers on the IC switch simultaneously. Excessive switching noise can cause both signal delays and possible false switching of adjacent logic gates. The capacitors act as local, temporarily independent energy sources to refresh or switch logic gates.
There are two applications here in reality: a) main supply-line bypass applications to reduce fluctuations caused by amps of power switching through supply-line inductances, and b) local integrated circuit (IC) bypass applications where capacitors are mounted very near ICs or blocks of ICs to reduce fluctuations caused by very fast, local current wave fronts.
4. Radio frequency applications include EMI filters, resonant circuits, matching networks, and a number of coupling/decoupling uses. One specific application is the use of capacitors in resonant converters of high voltage power supplies for traveling wave tubes. Another is the use of capacitors [and their inductive properties] to help xe2x80x9ctrimxe2x80x9d circuits.
5. High voltage power supplies, especially those with resonant converters, have high transformation ratios with many turns for secondary windings that induce high leakage inductance. Additional capacitor inductance must be minimized in order to minimize total system inductance and thus improve power usage factors and system efficiency.
6. The inductance of capacitors can be critical in capacitor-run and capacitor-start, single-phase and multi-phase motor applications. Shunt capacitors located across the terminals of stator windings in induction motors is one specific application. Other applications include circuits where capacitors are connected directly to the load-side of selected motor-starters in machine tool drives or capacitors in capacitor-start, single-phase, AC motors.
7. Inductance is also very important where capacitors act as energy sources for sudden energy discharges for systems, such as magnetic-pulse metal processing equipment, electromagnetic launchers, railguns, pulse welding equipmgent, pulse forming circuits, and magnetic pulse compressors (Konotop, V. V., xe2x80x9cLow-lnductance Capacitor,xe2x80x9d University of California Lawrence Radiation Lab, Translation, UCRL-TRANS-1273/L, 1965.).
8. Electricity generating agencies may mandate or provide incentives to improve the power factors of facilities or equipment (particularly overseas). A preferred approach is to install power factor correction capacitors to decrease reactive current. Installing such capacitors on equipment such as arc welders and arc furnaces requires parts with a minimum equivalent series inductance (Baroda, Anonymous, Devki R and D Engineers, xe2x80x9cSelection and Application of Capacitors,xe2x80x9d Electricity Conservation Quarterly, Vol. 10 (2), October 1989, pp. 3-6, 9.).
What Is The Inductance Of A Capacitor?
The equivalent series inductance (ESL) of the capacitor is usually thought to be an undesirable or xe2x80x9cparasiticxe2x80x9d property (however, in rare circuit timing applications the ESL is made use of). To understand inductance we must first discuss the simplified equivalent circuit model of a capacitor that is shown in FIG. 10 (a more complete model is shown in FIG. 13). This model consists of an ideal capacitor in series with an ESL and an equivalent series resistance (ESR). There is also a parallel resistance (not shown) due to the capacitors dielectric conductance. For this discussion, we shall ignore the capacitor""s insulation resistance (IR). This is because the typical IR (another parallel resistance) of modern capacitors is many hundreds of megohms or greater which does not significantly contribute to the operating impedance of the capacitor.
The capacitor""s impedance, Z, resonant frequency, ESL and ESR are defined by the following equations:       X    c    =                    -        j                    2        ⁢        π        ⁢                  xe2x80x83                ⁢        f        ⁢                  xe2x80x83                ⁢        C              =                  -        j                    ω        ⁢                  xe2x80x83                ⁢        C            
XL=+j2xcfx80fL=+jxcfx89L       SRF    =          1              2        ⁢        π        ⁢                  LC                          Z    =                                        (            ESR            )                    2                +                              (                                          X                L                            -                              X                C                                      )                    2                    
xe2x80x83Where:
xcfx89=the radian frequency
f=frequency in hertz
C=capacitance in farads
L=inductance (ESL) in henries
Xc=capacitive reactance in ohms
XL=inductive reactance in ohms
SRF=capacitor self resonant frequency in hertz.
Z=capacitor impedance in ohms
As can be seen, Z varies with frequency and reaches a minimum at the self-resonant frequency (SRF). Because it is such an important aspect of the capacitor""s impedance, we shall discuss ESR briefly before moving on to ESL. FIG. 11 is a vector diagram with real and imaginary axes which illustrates the relationship between the inductive and capacitor reactance, and the phase angle between the impedance and the real axis (ESR).
Equivalent Series Resistance (ESR)
The ESR of the capacitor is a lumped resistance parameter, which consists of many complicated elements. For a capacitor operating at low frequencies (such as 1 kHz) this resistance is a function of the dielectric loss tangent which is usually expressed as dissipation factor (DF). The ESR is also a function of ohmic losses due to connections, electrode material, electrode cross sectional area, leads, terminations, etc. At higher frequencies, skin effect plays an important role and can dominate ESR and the capacitor""s impedance.
For a given dielectric material, the capacitor designer actually can do very little to affect the DF (DF is primarily a property of the dielectric material selected). However, the designer can do a lot to control ESR, including selecting a specific capacitor form factor, electrode count, cross-sectional area and metallurgical quality of connections, and electrode and lead materials. ESR is generally considered an undesirable property which causes circuit power loss due to heat dissipation, raises the impedance, or affects the circuit time constant (t), thereby increasing capacitor charge-discharge time. The capacitor ESR is a function of frequency as illustrated in FIG. 12. (Ennis, J., xe2x80x9cCautions About the Use of Equivalent Series Resistance (ESR) in Specifying Capacitors,xe2x80x9d Proceedings. 13th Capacitor and Resistor Technology Symposium (CARTS ""93), Costa Mesa, Calif., March 1993, pp. 58-64.).
The Effect Of ESL On The Capacitor""s Impedance
For by-pass, EMI filter and RF coupling applications it is desirable for the capacitor""s impedance to be as low as possible. As a first step, the designer selects a high enough capacitance value so that the capacitive reactance will be very low at the frequencies of interest (in many cases close to zero ohms). In these cases, the impedance of the capacitor at operating frequencies is usually dominated by a combination of ESR and the inductive reactance due to ESL operating in series. FIG. 13 gives a more complete capacitor equivalent circuit which includes the dielectric conductance. Impedance, reactance, and resonance equations for this more complex capacitor model are provided by J. A. Sunda in his 1982 paper entitled xe2x80x9cMiniature Decoupling Capacitors for HF Applications (Sunda, J. A., xe2x80x9cMiniature Decoupling Capacitors for HF Applications,xe2x80x9d Australian Electronics Engineering Vol. 15, No. 7, Australia, July 1982, pp. 56-64.). As previously mentioned, the dielectric conductance is so low (IR is high) that the capacitor equivalent model illustrated in FIG. 10 is suitable for most prior art capacitor applications.
The Prior Art Capacitor At And Near Resonance
The simplified circuit model of the prior art capacitors shown in FIGS. 1-9 is a series circuit consisting of an R, L, and C. This means that there is a frequency at which +jXL and xe2x88x92jXc are of equal values in ohms. This is known as the capacitor""s self-resonant frequency (SRF), where the total impedance is at a minimum and is equal to the ESR. FIG. 14 is a graph of a typical impedance vs. frequency curve for a generic prior art capacitor. The solid line represents prior art capacitors. The ideal curve is illustrated by the dashed line. As can be seen, the impedance of the capacitor drops dramatically at the SRF.
There is also a reversal in the phase shift as the capacitor below resonance switches from capacitive behavior to inductive behavior above resonance. When this type of capacitor is used in an EMI filter application it is interesting to note that the insertion loss in dB reaches a maximum at the SRF. This is because the impedance of the capacitor is trying to go to 0xcexa9 at the SRF (the capacitor ESR prevents this).
At operating frequencies below the resonant frequency, the impedance of the capacitor appears capacitive with a phase shift wherein the current leads the voltage (if not for ESR, the current would lead the voltage by 90 degrees). At frequencies above resonance, the capacitor impedance appears increasingly inductive with a corresponding lag of the current relative to the voltage. At frequencies well above resonance, the capacitor impedance is completely dominated by inductive reactance which defeats the capacitor""s purpose in by-pass, EMI filtering, or RF coupling applications. Accordingly, knowing the capacitor SRF is a very important circuit design parameter.
FIG. 15, illustrates a prior art capacitor simplified equivalent circuit and a test model with a switch which was inspired from a paper by L. L. Macomber (Macomber, Laird, xe2x80x9cRipple/EMI Performance,xe2x80x9d Electron, May 22, 1979, pp. 15-18). Below the self resonant frequency, the prior art capacitor model is a capacitor in series with the ESR. At resonance, the capacitor model is a resistor (the ESR). Above resonance, the capacitor acts as an inductor in series with the ESR.
Low ESL Prior Art Capacitor Designs
The inductance of a conventionally manufactured capacitor is primarily a function of the magnetic loop area formed, for example, from lead to lead through the capacitor active area itself. The loop area (which determines ESL) is greatly affected by capacitor form factor and connections. For example, as shown in FIGS. 16a and 16b, a multilayer ceramic capacitor (MLC) chip 50 that is terminated along its opposite long sides with a narrow cross section (FIG. 16a) will have much lower ESL and ESR than a chip capacitor of equal value which is long and terminated on its short ends (FIG. 16b). The addition of leads or a frame lead 76 to a chip tends to increase ESL and ESR. Some prior art lead frame designs, however, are more efficient than others.
Table 1 is condensed from a study by Boser and Newsome which consisted of precise impedance measurements of side terminated vs. end terminated size 0805 MLC chip capacitors (Boser, Otmar and Newsome, Vernon, xe2x80x9cHigh Frequency Behavior of Ceramic Multilayer Capacitors,xe2x80x9d IEEE Transactions on Components, Hybrids, and Manufacturing Technology, Vol. CHMT-10 (3), September 1987, pp. 437-439). Of particular interest in this study are the significantly higher ESL values obtained for all of the end terminated configurations. A review of the data also indicates that the inductance varies very little with dielectric type or capacitance value. In general, MLC capacitors tend to have lower ESL than other technologies. This is due to the relatively high dielectric constant of ceramic capacitors and efficient electrode geometry. Chip (stack) plastic capacitors also have efficient electrode geometry and tend to be lower in ESL than wound capacitors. Because of the high dielectric constant, an MLC capacitor will be smaller in size for a given capacitance value than other technologies. The smaller size results in a significant reduction in ESL.
Form factor (length to width ratio) is also critical for low inductance and low ESR designs in both ceramic and plastic chip capacitors. Electrode alignment quality also affects chip ESL. Manufacturing methods, such as die punching and compaction, that result in greater accuracy of electrode alignment in the finished chip appear to reduce total chip inductance.
FIGS. 17 and 18 illustrate prior art feedthrough capacitors 86 and 88. Feedthrough capacitors are very low inductance devices which cannot be modeled with lumped parameters. They are best modeled as a transmission line and exhibit excellent high frequency performance. However, feedthrough capacitors are designed to be mounted on a bulkhead, terminal or housing, therefore, they are not suitable for most substrate or circuit board mounting applications.
FIGS. 19a-19c illustrate a prior art flat-thru style capacitor 90. Flat-thru capacitors 90 are also very low inductance devices which cannot be modeled with lumped parameters. As for feedthrough capacitors 86 and 88, they are best modeled as a transmission line and also exhibit excellent high frequency performance. Flat-thru capacitors 90 are well suited for substrate or circuit board mounting, however, they are very limited in the amount of current that they can handle. This is because the circuit current must pass entirely through the electrodes themselves which are thin and lacy. In general, the flat-thru design is not used in high current applications, such as the output circuitry of a SMPS because of these current limitations.
Discussion Of Prior Art Capacitor Circuit Installation
For all capacitor technologies, leads and circuit layout contribute greatly to ESL by increasing the overall magnetic loop area. Correspondingly, wire-bonded connections tend to introduce much more inductance than soldered or conductive epoxy-bonded land connections.
The contribution to inductance from leads and wire-bonded connections can be estimated from the equation for the inductance of a straight round wire (Breed, Gary A., xe2x80x9cCapacitor Behavior at Radio Frequencies,xe2x80x9d RF Design. Vol. 19 (1), January 1996, pp. 58-61).
L=0.0002b[In(2b/a)xe2x88x920.75]
Where L is the inductance in xcexcH, a is the wire radius in mm, and b is the wire length in mm.
For example: a xc2xc inch (6.3 mm) length of #20 AWG (0.8 mm) wire has an inductance of 3.4 nH (Breed, Gary A., xe2x80x9cCapacitor Behavior at Radio Frequencies,xe2x80x9d RF Design, Vol. 19 (1), January 1996, pp. 58-61.).
In actual practice, when leads are in close proximity to other circuit""s elements, a more complex analysis may be required. An approximate guideline for leaded parts has been offered by Harrop (Harrop, P. J., xe2x80x9cRadio Frequency Capacitors,xe2x80x9d Electron, No. 68, 13, Feb. 1975, pp. 56, 58, 61.) who states that radial leaded capacitors are limited to applications of 10 MHz or below. This is due to their relatively short leads, while axial leaded parts are limited to 5 MHZ because their leads must have a right angle bend for PWA mounting and are, therefore, double the length.
Multiple bus bar or multiple tab designs significantly reduce ESL. Tabs, or bus bars, have lower inductance than wires due to their width. Multiple tabs reduce electrode displacement current density which reduces capacitor internal inductance. Four terminal designs eliminate the effect of tab inductance (Macomber, Laird, xe2x80x9cRipple/EMI Performance,xe2x80x9d Electron, May 22, 1979, pp. 15-18.). FIG. 20 and FIGS. 21a-21d illustrate prior art capacitor designs which reduce ESL. For example, conventionally designed Al-electrolytic capacitors exhibit ESL in the nanohenry range; whereas, 4-terminal designs (see Table 2) exhibit ESL in the microhenry range (Macomber, Laird, xe2x80x9cRipple/EMI Performance,xe2x80x9d Electron, May 22, 1979, pp. 15-18). As previously mentioned, capacitor ESL (and ESR) is primary a funtion of capacitor design and construction. Selection of dielectric and electrode materials is usually a much smaller effect.
FIG. 20 shows a cross section of a prior art Low Inductance Capacitors Array (LICA) capacitor 92 (arrows show direction of electrode displacement currents) (Galvagni, John, et al., xe2x80x9cSo Many Electrons, So Little Time . . . ,xe2x80x9d Proceedings, 44th Electronic Components and Technology Conference, 1994, pp. 234-238.).
FIGS. 21a-21d show how proper tab construction can reduce ESL in Al-electrolytic capacitors 94 (Macomber, Laird, xe2x80x9cRipple/EMI Performance,xe2x80x9d Electron, May 22, 1979, pp. 15-18).
Table 2. ESL vs. Al Construction Style
H. Vetter, (Vetter, Harold, xe2x80x9cHigh-Performance Capacitors for Low-Inductance Circuits,xe2x80x9d Siemens Components, Vol 25 (3), 1990, pp. 81-85. Also in Proceedings, 22nd International Power Conversion Conference (PCIM), 1991, Europe, pp. 141-148.), points out a number of other construction details in Al foil capacitors (and other-wound paper and metallized capacitors) that directly affect inductance as well as tab designs. Having multiple, large-area connections to thick electrode foils, coaxial winding of electrodes in separate layers, controlling the capacitor height/width ratio and use of cylindrical vs. circular cross-sectional areas, will all affect inductance.
Discrete component location in integrated components, such as filters, temperature-compensated oscillator circuits and delay lines also affects ESL. Proper location and mounting configuration of capacitors and magnetic components with respect to each other and to substrate metallization patterns will reduce total device ESL.
Capacitor design optimization should be matched with circuit layout optimization. Schaper and Morcan, (Schaper, Leonard W. and Morcan, Gabriel, xe2x80x9cHigh Frequency Characteristics of MCM Decoupling Capacitors,xe2x80x9d Proceedings, 46th Electronic Components and Technology Conference, Las Vegas, Nev., 1996, pp. 358-364.), provide the following inductance values for surface mount technology connections:
short wirebond xcx9c1 nH
solder bumps and pedestals xcx9c0.05 nH
PC traces xcx9c10 nH/inch1 
A comparison of interconnection techniques, including wire bonding, Tape Automated Bonding, and gold bump bonding, with respect to their relative inductance is provided by Galvagni and co-authors (Galvagni, John, et al., xe2x80x9cSo Many Electrons, So Little Time . . . ,xe2x80x9d Proceedings, 44th Electronic Components and Technology Conference, 1994, pp. 234-238.).
Ceramic capacitors are particularly appropriate for low ESL applications because of their high unit capacitance provided in a small size combined with robust construction. The high dielectric constant of ceramic capacitors reduces their volume, which also tends to reduce the ESL and ESR.
Ceramic capacitors are typically constructed by interleaving nonconductive layers of high dielectric constant ceramic material with metallic electrodes. The metallic electrodes are typically xe2x80x9clayed-downxe2x80x9d on the green ceramic material by silk screening processes. The device is then fired (sintered) to form a rugged monolithic structure (the xe2x80x9ccapacitorxe2x80x9d). Monolithic ceramic capacitors are well known in the art for a variety of applications in both surface mount (chip capacitor) and leaded applications. Also well known in the art are stacked film capacitors, which are constructed in a very similar manner to ceramic chip capacitors. Layers of film dielectric are interleaved with conductive electrodes, thereby forming a chip-type capacitor. Tantalum, aluminum electrolytic or wound/stacked film capacitors are generally not as low in ESL and ESR as a ceramic capacitor since they tend to be larger due to their lower dielectric constant.
Capacitor manufacturers have come up with many novel designs to reduce inductance. However, these designs have involved methods of making multiple attachments to the electrodes so that the interconnection inductances are reduced or the interconnection resistance is reduced.
FIGS. 22 and 23 illustrate use of a typical capacitor array 74 similar to that illustrated in FIGS. 7 and 8, as utilized in connection with a switch mode power supply (SMPS) 96. The exemplary SMPS 96 of FIG. 22 includes a housing 98 in which a circuit board 100 is placed. An AC plug 102 is accessible through the housing 98 and provides power to the components mounted on the circuit board 100. The capacitor array 74 is conductively coupled to circuit traces 104 which extend to output terminals 106. FIG. 23 illustrates how the circuit model (FIG. 10) of the capacitor array 74 extends. between the circuit traces 104 intermediate the primary components of the switch mode power supply 96 and the output terminals 106.
In view of all of the foregoing, it is clear that there is a need for an improved capacitor design which dramatically reduces the inductance and ESR of the device, thereby improving its high frequency performance. Further, an improved capacitor design is needed which is particularly suited to the type of monolithic ceramic stacked capacitors that are used in surface mount power supplies, buck regulators and DC to DC converters to control output ripple current. Moreover, an improved capacitor design is needed which is capable of routing circuit current past the capacitor""s inductance such that it is no longer in series. This would result in a dramatic improvement in the bypassing or attenuation of high frequency ripple or fast rise time pulses. The present invention fulfills these needs and provides other related advantages
The present invention resides in a novel capacitor transmission line lead frame which incorporates a unique configuration that routes the output (or input) current of an electronic device through the capacitor. This technique turns the capacitor from a two terminal device into a four terminal network, which acts as a transmission line. This has the effect of dramatically reducing the capacitor inductance (ESL) and is also very effective in reducing ESR. In addition, the novel transmission line lead frame is particularly suited for surface mounting or through hole mounting so that it is compatible with other component installation techniques. Another advantage of the invention is that low cost, high volume chip capacitors which are well known in the art, are readily adaptable to mounting with this lead frame approach. This results in substantial cost savings over other transmission line style capacitors, for example feedthrough capacitor technology.
More particularly, the present invention resides in a capacitor which comprises a casing of dielectric material having first and second sets of electrode plates disposed therein, a first conductive lead frame conductively coupled to the first set of electrode plates, and a second conductive lead frame conductively coupled to the second set of electrode plates. The first conductive lead frame includes a first connector which is attachable to a first circuit trace of an integrated circuit and second connector attachable to a second circuit trace of the integrated circuit such that the first conductive lead frame conductively couples the first circuit trace to the second circuit trace. The second conductive lead frame includes a first connector attachable to a third circuit trace of the integrated circuit and a second connector attachable to a fourth circuit trace of the integrated circuit such that the second conductive lead frame conductively couples the third circuit trace to the fourth circuit trace.
Typically a first metallization band is disposed along one side of the casing and is conductively coupled to the first set of electrode plates. Similarly, a second metallization band is disposed along another side of the casing and is conductively coupled to the second set of electrode plates. In several of the illustrated embodiments herein, the first and second lead frames are conductively coupled to, respectively, the first and second metallization bands. However, the first and second metallization bands may form, respectively, the first and second lead frames themselves.
The advantages of the novel capacitor transmission lead frame include: A) complete reduction or elimination of the capacitor external inductance due to leads and connection techniques (a small amount of capacitor internal inductance is all that remains); B) reduction in ESR due to the efficient electrode geometry and method of routing circuit input (or output) current through the capacitor; C) greatly improved RF performance at high frequency (the transmission line style lead frame is particularly effective for controlling the ripple effect of high frequency switch mode power supplies, or other high frequency applications); D) a significantly increased capacitor self resonant frequency (SRF); and E) the unique configurations of the capacitor transmission line lead frame gives a designer the ability to place the capacitor at strategic locations on a substrate near the point of lead ingress or egress. This latter point is particularly important when said chips are mounted at a distance from the shield can or housing or point of entry, point of ingress or egress from an electronic device. High frequency ripple or noise can couple across some of said components and recouple to other parts of the circuit.
A feature of the invention is that the input or output current of the electronic circuit or device must pass through the lead frame itself. This is very unlike a conventional capacitor, which conducts no current (other than charging current) in a DC circuit application, or conducts only capacitor reactive current in an AC application. Since the novel capacitor lead frame as described herein turns the chip capacitor into a four terminal device the lead frame must carry the entire circuit current. Accordingly, the lead frame must be sized as to thickness, length, and width so as to carry the output current or input current without overheating or fusing.
The novel transmission line style lead frame of the present invention can be constructed of a variety of conductive materials including copper, brass, plated steel, aluminum, and other metals. The designer also has a wide choice of finishes or platings or surface finishes. Typical examples would be nickel and electro-tin plating, silver plating, hot solder dipping, or gold plating. A wide variety of mounting tabs are possible (a few have been illustrated in the accompanying drawings). It will be obvious to one skilled in the art that mounting tabs can be constructed for mounting to a substrate by through hole soldering, surface mounting by soldering or conductive thermal setting adhesives, wire-bonding, mounting by screws or fasteners or by welding, or the like.
The method of attachment between the capacitor and the lead frame can also be accomplished through with a variety of materials and construction techniques. Monolithic ceramic capacitors are typically terminated with either a silver or palladium silver bearing glass frit which is fired onto the capacitor (there are alternative terminations including plated nickel, gold, etc.). The capacitor terminations connect the internal electrode plates in parallel and also provide a solderable electrically conductive finish for lead attachment. Accordingly, leads may be attached by solder, conductive adhesives, or other electrical bonding techniques. In a similar manner, film capacitors which are stacked as chips are typically terminated by spraying babbitt or other conductive material to connect their internal electrode plate sets in parallel. Accordingly, the transmission line style lead frame can be attached in the same manner as previously described for the monolithic ceramic capacitor.